A concurrent error detection and correction based fault-tolerant xor-xnor circuit for highly reliable applications

The continuous shrinking of MOS devices dimensions affects the circuit performance and reliability by introducing transient and permanent faults that can cause critical failures which make Fault-tolerant VLSI integrated circuits a typical requirement especially in safety-critical applications. Thus, in this work, we address the issue of fault-tolerant chip based on using Concurrent Error Detection and Correction architectures. Since XORXNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate and correct any malfunction during normal operation. In fact, the property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED) while the property of correcting a considered fault during normal operation is called Concurrent Error Correction (CEC). In this work, we propose a concurrent error detection and correction based fault-tolerant XOR-XNOR circuit implementation. The proposed design is implemented using the 32 nm process technology.