RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

Sang Lam; Hui Wan; Pin Su; Peter W. Wyatt; C. L. Chen; Ali M. Niknejad; Chenming Hu; Ping K. Ko; Mansun Chan

doi:10.1109/LED.2003.810892

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

Sang Lam^*
, Hui Wan
, Pin Su
, Peter W. Wyatt
, C. L. Chen
, Ali M. Niknejad
, Chenming Hu
, Ping K. Ko
, Mansun Chan

^*Corresponding author for this work

University of California at Berkeley
Hong Kong University of Science and Technology
Massachusetts Institute of Technology

Research output: Contribution to journal › Letter › peer-review

10 Citations (Scopus)

Abstract

The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance R_G, the metal T-gate FD-SOI MOSFET achieves a higher f_max of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower f_T of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances C_gs and C_gd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

Original language	English
Pages (from-to)	251-253
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	24
Issue number	4
DOIs	https://doi.org/10.1109/LED.2003.810892
Publication status	Published - 1 Apr 2003
Externally published	Yes

Keywords

Fully-depleted SOI MOSFET
Metal gate
RF CMOS
T-gate structure

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10.1109/LED.2003.810892

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@article{38806daa0c974433ae942fac96bf7183,

title = "RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology",

abstract = "The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance RG, the metal T-gate FD-SOI MOSFET achieves a higher fmax of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower fT of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40\% and 80\% increase in the parasitic capacitances Cgs and Cgd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.",

keywords = "Fully-depleted SOI MOSFET, Metal gate, RF CMOS, T-gate structure",

author = "Sang Lam and Hui Wan and Pin Su and Wyatt, \{Peter W.\} and Chen, \{C. L.\} and Niknejad, \{Ali M.\} and Chenming Hu and Ko, \{Ping K.\} and Mansun Chan",

note = "Funding Information: Manuscript received January 13, 2003. This work was supported in part by the Semiconductor Research Corporation under Contract 2000-NJ-795, the Defense Advanced Research Projects Agency Air Force Contract F19628–00-C-0002, and an earmarked grant from the Research Grant Council of Hong Kong under Contract HKUST6236/00E. The review of this letter was arranged by Editor A. Chatterjee.",

year = "2003",

month = apr,

day = "1",

doi = "10.1109/LED.2003.810892",

language = "English",

volume = "24",

pages = "251--253",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

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}

TY - JOUR

T1 - RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

AU - Lam, Sang

AU - Wan, Hui

AU - Su, Pin

AU - Wyatt, Peter W.

AU - Chen, C. L.

AU - Niknejad, Ali M.

AU - Hu, Chenming

AU - Ko, Ping K.

AU - Chan, Mansun

N1 - Funding Information: Manuscript received January 13, 2003. This work was supported in part by the Semiconductor Research Corporation under Contract 2000-NJ-795, the Defense Advanced Research Projects Agency Air Force Contract F19628–00-C-0002, and an earmarked grant from the Research Grant Council of Hong Kong under Contract HKUST6236/00E. The review of this letter was arranged by Editor A. Chatterjee.

PY - 2003/4/1

Y1 - 2003/4/1

N2 - The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance RG, the metal T-gate FD-SOI MOSFET achieves a higher fmax of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower fT of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances Cgs and Cgd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

AB - The metal T-gate structure in fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is investigated from the RF perspective. With the expected low gate resistance RG, the metal T-gate FD-SOI MOSFET achieves a higher fmax of 67 GHz as compared with 12.5 GHz in the silicided polysilicon gate counterpart. However, the metal T-gate FD-SOI MOSFET has a lower fT of 35 GHz as compared with 44 GHz for the self-aligned polysilicon gate. The extracted parameters reveal that the T-gate structure results in an extra 40% and 80% increase in the parasitic capacitances Cgs and Cgd respectively. The metal gate structure together with the source-drain structure have to be co-optimized to boost the RF performance of FD-SOI MOSFET. A simple guideline to optimize the structure is included.

KW - Fully-depleted SOI MOSFET

KW - Metal gate

KW - RF CMOS

KW - T-gate structure

UR - https://www.scopus.com/pages/publications/0038781379

U2 - 10.1109/LED.2003.810892

DO - 10.1109/LED.2003.810892

M3 - Letter

AN - SCOPUS:0038781379

SN - 0741-3106

VL - 24

SP - 251

EP - 253

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 4

ER -

RF characterization of metal T-gate structure in fully-depleted SOI CMOS technology

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