Process algebraic specification of DI circuits

Ka Lok Man; Abhinav Asthana; Hemangee K. Kapoor; Tomas Krilavičius; Jian Chang

doi:10.1109/SOCDC.2010.5682885

Process algebraic specification of DI circuits

Ka Lok Man
, Abhinav Asthana
, Hemangee K. Kapoor
, Tomas Krilavičius
, Jian Chang

Department of Computing

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

1 Citation (Scopus)

Abstract

The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.

Original language	English
Title of host publication	2010 International SoC Design Conference, ISOCC 2010
Publisher	IEEE Computer Society
Pages	396-399
Number of pages	4
ISBN (Print)	9781424486335
DOIs	https://doi.org/10.1109/SOCDC.2010.5682885
Publication status	Published - 2010

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Name	2010 International SoC Design Conference, ISOCC 2010

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10.1109/SOCDC.2010.5682885

Cite this

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title = "Process algebraic specification of DI circuits",

abstract = "The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.",

author = "Man, \{Ka Lok\} and Abhinav Asthana and Kapoor, \{Hemangee K.\} and Tomas Krilavi{\v c}ius and Jian Chang",

year = "2010",

doi = "10.1109/SOCDC.2010.5682885",

language = "English",

isbn = "9781424486335",

series = "2010 International SoC Design Conference, ISOCC 2010",

publisher = "IEEE Computer Society",

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Process algebraic specification of DI circuits. / Man, Ka Lok; Asthana, Abhinav; Kapoor, Hemangee K. et al.
2010 International SoC Design Conference, ISOCC 2010. IEEE Computer Society, 2010. p. 396-399 5682885 (2010 International SoC Design Conference, ISOCC 2010).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - Process algebraic specification of DI circuits

AU - Man, Ka Lok

AU - Asthana, Abhinav

AU - Kapoor, Hemangee K.

AU - Krilavičius, Tomas

AU - Chang, Jian

PY - 2010

Y1 - 2010

N2 - The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.

AB - The purpose of this paper is to investigate applicability of Null Conventional Logic (NCL) for synthesising asynchronous control circuits using. The target implementation being delay insensitive (DI), the specification language also should be DI. Delay Insensitive Sequential Processes (DISP) is such a process algebraic language where the behaviour of asynchronous control logic blocks can be expressed as processes. We have mapped several basic DISP constructs to NCL and performed a small cases study. It is a step towards an alternative synthesis way for NCL circuits.

UR - https://www.scopus.com/pages/publications/79851486033

U2 - 10.1109/SOCDC.2010.5682885

DO - 10.1109/SOCDC.2010.5682885

M3 - Conference Proceeding

AN - SCOPUS:79851486033

SN - 9781424486335

T3 - 2010 International SoC Design Conference, ISOCC 2010

SP - 396

EP - 399

BT - 2010 International SoC Design Conference, ISOCC 2010

PB - IEEE Computer Society

ER -

Process algebraic specification of DI circuits

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