TY - GEN
T1 - Physics-AI-Driven Design of GaN P-MISFETs with InGaN/AlN/AlGaN Heterostructures
AU - Sun, Linkun
AU - Hu, Zhehao
AU - Guo, Qiyi
AU - Li, Bowen
AU - Low, Kain Lu
AU - Liu, Wen
N1 - Publisher Copyright:
© 2026 IEEE.
PY - 2026/5/6
Y1 - 2026/5/6
N2 - This paper presents a hybrid physics-AI framework for the design of CMOS-compatible p-type GaN MISFETs based on a polarization-engineered InGaN/AlN/AlGaN/AlN/GaN heterostructure. The workflow combines TCAD simulations, design of experiments (DOE), clustering analysis, and SHAP-informed feature evaluation to identify key design parameters and trade-offs. Results reveal that recess depth is the dominant factor, improving subthreshold swing (SS) and boosting Ion but shifting Vth negatively. In contrast, an AlN interlayer and higher Al/In compositions raise Vth via stronger polarization but degrade transport through reduced hole velocity and screening. SHAP analysis confirms these trade-offs, underscoring the need for co-optimization of recess depth, material composition, and interlayer design to balance Ion, SS, and Vth in GaN CMOS technology.
AB - This paper presents a hybrid physics-AI framework for the design of CMOS-compatible p-type GaN MISFETs based on a polarization-engineered InGaN/AlN/AlGaN/AlN/GaN heterostructure. The workflow combines TCAD simulations, design of experiments (DOE), clustering analysis, and SHAP-informed feature evaluation to identify key design parameters and trade-offs. Results reveal that recess depth is the dominant factor, improving subthreshold swing (SS) and boosting Ion but shifting Vth negatively. In contrast, an AlN interlayer and higher Al/In compositions raise Vth via stronger polarization but degrade transport through reduced hole velocity and screening. SHAP analysis confirms these trade-offs, underscoring the need for co-optimization of recess depth, material composition, and interlayer design to balance Ion, SS, and Vth in GaN CMOS technology.
UR - https://ieeexplore.ieee.org/abstract/document/11497062
UR - https://www.scopus.com/pages/publications/105040805295
U2 - 10.1109/EDTM65772.2026.11497062
DO - 10.1109/EDTM65772.2026.11497062
M3 - Conference Proceeding
AN - SCOPUS:105040805295
T3 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
BT - 10th IEEE Electron Devices Technology and Manufacturing Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th IEEE Electron Devices Technology and Manufacturing Conference: Emerging Semiconductor Devices and Manufacturing Technologies, EDTM 2026
Y2 - 1 March 2026 through 4 March 2026
ER -