PAFSV: A formal framework for specification and analysis of SystemVerilog

Ka Lok Man; Chi Un Lei; Hemangee K. Kapoor; Tomas Krilavičius; Jieming Ma; Nan Zhang

PAFSV: A formal framework for specification and analysis of SystemVerilog

Ka Lok Man, Chi Un Lei, Hemangee K. Kapoor, Tomas Krilavičius, Jieming Ma, Nan Zhang

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800^™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800^™ SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800^™ SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter.

Original language	English
Pages (from-to)	143-176
Number of pages	34
Journal	Computing and Informatics
Volume	35
Issue number	1
Publication status	Published - 2016

Keywords

Circuit verification
Formal semantics
Formal specification and analysis
PAFSV
Process algebras
SystemVerilog

Cite this

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title = "PAFSV: A formal framework for specification and analysis of SystemVerilog",

abstract = "We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800{\texttrademark} SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800{\texttrademark} SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800{\texttrademark} SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter.",

keywords = "Circuit verification, Formal semantics, Formal specification and analysis, PAFSV, Process algebras, SystemVerilog",

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AU - Kapoor, Hemangee K.

AU - Krilavičius, Tomas

AU - Ma, Jieming

AU - Zhang, Nan

PY - 2016

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AB - We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800™ SystemVerilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800™ SystemVerilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter.

KW - Circuit verification

KW - Formal semantics

KW - Formal specification and analysis

KW - PAFSV

KW - Process algebras

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EP - 176

JO - Computing and Informatics

JF - Computing and Informatics

IS - 1

ER -

PAFSV: A formal framework for specification and analysis of SystemVerilog

Abstract

Keywords

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