TY - JOUR
T1 - Optimization of 6T-SRAM Cell Based on CNN-Informed NSGA-II with Consideration of Parasitic Resistance
AU - Zheng, Qiwen
AU - Wu, Ye
AU - Zhao, Chun
AU - Zhou, Jiafeng
PY - 2025/10/13
Y1 - 2025/10/13
N2 - Optimizing static random-access memory (SRAM) cells requires considering parasitic effects, as their impact on circuits in advanced nodes becomes increasingly complex. In this paper, Convolutional Neural Network-Informed Non-dominated Sorting Genetic Algorithms-II (CNN-Informed NSGA-II) was proposed to optimize 7 nm FinFET 6T-SRAM cells taking into account parasitic resistance. CNN-Informed NSGA-II uses a trained CNN model integrated into the conventional NSGA-II, thereby reducing its computational complexity. This approach provides a generally applicable solution that significantly improves the efficiency of circuits while balancing competitive performance metrics. Compared to the ideal (parasitic-free) 6T-SRAM cell design, the optimized 6T-SRAM cell design (considering parasitic effects) achieves a reduction of 81.60% in Write Dynamic Power and 64.65% in Write Time; HSNM and RSNM are improved by 11.92% and 6.42%, respectively. The optimized 7 nm FinFET 6T-SRAM cell structure in this paper outperforms the parasitic-free structure in terms of the performance parameters above, even when taking into account parasitic effects.
AB - Optimizing static random-access memory (SRAM) cells requires considering parasitic effects, as their impact on circuits in advanced nodes becomes increasingly complex. In this paper, Convolutional Neural Network-Informed Non-dominated Sorting Genetic Algorithms-II (CNN-Informed NSGA-II) was proposed to optimize 7 nm FinFET 6T-SRAM cells taking into account parasitic resistance. CNN-Informed NSGA-II uses a trained CNN model integrated into the conventional NSGA-II, thereby reducing its computational complexity. This approach provides a generally applicable solution that significantly improves the efficiency of circuits while balancing competitive performance metrics. Compared to the ideal (parasitic-free) 6T-SRAM cell design, the optimized 6T-SRAM cell design (considering parasitic effects) achieves a reduction of 81.60% in Write Dynamic Power and 64.65% in Write Time; HSNM and RSNM are improved by 11.92% and 6.42%, respectively. The optimized 7 nm FinFET 6T-SRAM cell structure in this paper outperforms the parasitic-free structure in terms of the performance parameters above, even when taking into account parasitic effects.
U2 - 10.3390/electronics14204002
DO - 10.3390/electronics14204002
M3 - Article
SN - 2079-9292
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
ER -