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Monolithically integrated GaN hysteresis comparator based on complementary logic

  • Shaoyan Ma*
  • , Qimeng Jiang*
  • , Sen Huang*
  • , Yang Yang
  • , Xuanming Zhang
  • , Jianfei Liu
  • , Xinhua Wang
  • , Ke Wei
  • , Xinguo Gao
  • , Lizhao Cen
  • , Wen Liu*
  • , Xinyu Liu
  • *Corresponding author for this work
  • CAS - Institute of Microelectronics
  • Southwest Jiaotong University
  • Xi'an Jiaotong-Liverpool University
  • University of Liverpool
  • Department of Electrical and Electronic Engineering and School of Advanced Technology

Research output: Contribution to journalArticlepeer-review

Abstract

A monolithically integrated gallium nitride (GaN) hysteresis comparator based on complementary logic (CL) architecture is demonstrated on a GaN-on-Si platform. The proposed circuit integrates a first-stage comparator, a second-stage inverter buffer, and a feedback network to generate a hysteresis window. At VDD = 6 V, the fabricated hysteresis comparator achieves an output swing of ∼5.8 V and a hysteresis window of ∼1.5 V. Transient voltage waveforms at critical circuit nodes are measured and analyzed to elucidate the impact of GaN n/p-channel field-effect transistor (n/p-FET) performance mismatch on circuit operation. The analysis reveals that the low current density and threshold voltage shifts of p-FETs limit the switching precision and slew rate. Based on these findings, strategies for performance enhancement are identified from both device processing and circuit design perspectives. These results provide valuable insights for the further development of GaN CL integrated circuits for next-generation power conversion systems.

Original languageEnglish
Article number055024
JournalSemiconductor Science and Technology
Volume41
Issue number5
DOIs
Publication statusPublished - May 2026

Keywords

  • complementary logic
  • GaN
  • hysteresis comparator
  • integrated circuit
  • p-FET

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