Minimal instruction set AES processor using Harvard architecture

J. H. Kong; L. M. Ang; K. P. Seng

doi:10.1109/ICCSIT.2010.5564522

Minimal instruction set AES processor using Harvard architecture

J. H. Kong
, L. M. Ang
, K. P. Seng

Materials and Manufacturing Engineering

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

4 Citations (Scopus)

Abstract

This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.

Original language	English
Title of host publication	Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Pages	65-69
Number of pages	5
DOIs	https://doi.org/10.1109/ICCSIT.2010.5564522
Publication status	Published - 2010
Externally published	Yes
Event	2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 - Chengdu, China Duration: 9 Jul 2010 → 11 Jul 2010

Publication series

Name	Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Volume	9

Conference

Conference	2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010
Country/Territory	China
City	Chengdu
Period	9/07/10 → 11/07/10

Keywords

Aes
Computer security
Minimal instruction set computer

Access to Document

10.1109/ICCSIT.2010.5564522

Cite this

Kong, J. H., Ang, L. M., & Seng, K. P. (2010). Minimal instruction set AES processor using Harvard architecture. In Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 (pp. 65-69). Article 5564522 (Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010; Vol. 9). https://doi.org/10.1109/ICCSIT.2010.5564522

@inproceedings{17389287af874d6f9fd3aff0a3ab37ba,

title = "Minimal instruction set AES processor using Harvard architecture",

abstract = "This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 \% of the total available chip area.",

keywords = "Aes, Computer security, Minimal instruction set computer",

author = "Kong, \{J. H.\} and Ang, \{L. M.\} and Seng, \{K. P.\}",

year = "2010",

doi = "10.1109/ICCSIT.2010.5564522",

language = "English",

isbn = "9781424455386",

series = "Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010",

pages = "65--69",

booktitle = "Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010",

note = "2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 ; Conference date: 09-07-2010 Through 11-07-2010",

}

Kong, JH, Ang, LM & Seng, KP 2010, Minimal instruction set AES processor using Harvard architecture. in Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010., 5564522, Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, vol. 9, pp. 65-69, 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010, Chengdu, China, 9/07/10. https://doi.org/10.1109/ICCSIT.2010.5564522

Minimal instruction set AES processor using Harvard architecture. / Kong, J. H.; Ang, L. M.; Seng, K. P.
Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010. 2010. p. 65-69 5564522 (Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010; Vol. 9).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - Minimal instruction set AES processor using Harvard architecture

AU - Kong, J. H.

AU - Ang, L. M.

AU - Seng, K. P.

PY - 2010

Y1 - 2010

N2 - This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.

AB - This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 % of the total available chip area.

KW - Aes

KW - Computer security

KW - Minimal instruction set computer

UR - https://www.scopus.com/pages/publications/77958616527

U2 - 10.1109/ICCSIT.2010.5564522

DO - 10.1109/ICCSIT.2010.5564522

M3 - Conference Proceeding

AN - SCOPUS:77958616527

SN - 9781424455386

T3 - Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010

SP - 65

EP - 69

BT - Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010

T2 - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010

Y2 - 9 July 2010 through 11 July 2010

ER -

Kong JH, Ang LM, Seng KP. Minimal instruction set AES processor using Harvard architecture. In Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010. 2010. p. 65-69. 5564522. (Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010). doi: 10.1109/ICCSIT.2010.5564522

Minimal instruction set AES processor using Harvard architecture

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this