Layout-Configurable and Low-Loss Impedance Matching Circuits Built of Slim CMOS Transmission Lines

Hongyu Bao, Yuxin Chu, Sang Lam

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

2 Citations (Scopus)

Abstract

Using slim on-chip transmission lines of a compact multi-metallization structure, millimeter-wave impedance matching circuits are constructed by two open stubs. In a typical 50-Ω system, an impedance transformation ratio of 1:5 is achieved by configuring multiple transmission line segments of 60.5 Ω, 32.5 Ω and 50 Ω in their characteristic impedance Z0. Based on a 65-nm CMOS process, the design gives an insertion loss of 1.0 dB at 60 GHz, according to 3D electromagnetic simulation. The reflection loss is also fairly low with |S11| ≈ -16 dB. The low-loss impedance transformer has a broad bandwidth of 25.6 GHz for |S11| < -10 dB. The bandwidth is also broad in a simple quarter-wavelength transformer but with about 1.4 dB insertion loss. With its compact structure, the layout of the transmission line segments can be easily configured to fit the floor-planning of a millimeter-wave integrated circuit, occupying a minimal chip area (< 17 μm in width).

Original languageAmerican English
Title of host publicationProceedings of 2022 IEEE International Conference on IC Design and Technology, ICICDT 2022
EditorsXuan-Tu Tran, Duy-Hieu Bui
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages40-43
Number of pages4
ISBN (Electronic)9781665459013
DOIs
Publication statusPublished - 2022

Publication series

NameProceedings of IEEE International Conference on IC Design and Technology, ICICDT

Keywords

  • CMOS transmission line
  • impedance matching circuits
  • impedance transformation
  • millimeter-wave integrated circuits

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