High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance

Jingyue Wu; Qiyi Guo; Xuanming Zhang; Jiachen Duan; Hao Wang; Jiangmin Gu; Wen Liu

doi:10.1109/CSTIC68613.2026.11537913

High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance

Jingyue Wu
, Qiyi Guo
, Xuanming Zhang
, Jiachen Duan
, Hao Wang
, Jiangmin Gu
, Wen Liu^*

^*Corresponding author for this work

Xi'an Jiaotong-Liverpool University
University of Liverpool
Advanced Semiconductor Research Center

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

Abstract

In this work, we present AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MIS-HEMTs) with an AlN/Al₂O₃ gate dielectric intended for high-voltage GaN power applications with low dynamic ON-resistance (R_ON) and stable threshold voltage (V_th). The high-quality plasma-enhanced atomic layer deposition (PEALD) AlN insert layer effectively reduces interface traps and suppresses charge trapping effects, enabling the MIS-HEMTs to exhibit a low dynamic R_ON degradation of only 2.77 times after 300 ms drain bias stress, significantly lower than the 4.2 times observed in conventional Al₂O₃ gate stacks. Under negative bias temperature instability (NBTI) stress with V_GS = -16 V for 10⁴ s, the V_th shift is less than 0.14 V, indicating superior reliability under long-term negative gate bias. Furthermore, a negligible V_th shift is observed under positive gate bias conditions.

Original language	English
Title of host publication	2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026
Editors	Cor Claeys, Bin Yu, Beichao Zhang, Peng Bai, Qianqian Huang, Xiaowei Li, Steve X. Liang, Hsiang-Lan Lung, Linyong Pang, Xinping Qu, Xiaoping Shi, Jianshi Tang, Pingqiang Zhou, Cheng Zhuo
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331592745
DOIs	https://doi.org/10.1109/CSTIC68613.2026.11537913
Publication status	Published - 2026
Event	2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026 - Shanghai, China Duration: 22 Mar 2026 → 24 Mar 2026

Publication series

Name	2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026

Conference

Conference	2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026
Country/Territory	China
City	Shanghai
Period	22/03/26 → 24/03/26

Keywords

AlN
Dynamic R
Interface Trap Density
MIS-HEMT
NBTI
Reliability

Access to Document

10.1109/CSTIC68613.2026.11537913

Cite this

Wu, J., Guo, Q., Zhang, X., Duan, J., Wang, H., Gu, J., & Liu, W. (2026). High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance. In C. Claeys, B. Yu, B. Zhang, P. Bai, Q. Huang, X. Li, S. X. Liang, H.-L. Lung, L. Pang, X. Qu, X. Shi, J. Tang, P. Zhou, & C. Zhuo (Eds.), 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026 (2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSTIC68613.2026.11537913

Wu, Jingyue ; Guo, Qiyi ; Zhang, Xuanming et al. / High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance. 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026. editor / Cor Claeys ; Bin Yu ; Beichao Zhang ; Peng Bai ; Qianqian Huang ; Xiaowei Li ; Steve X. Liang ; Hsiang-Lan Lung ; Linyong Pang ; Xinping Qu ; Xiaoping Shi ; Jianshi Tang ; Pingqiang Zhou ; Cheng Zhuo. Institute of Electrical and Electronics Engineers Inc., 2026. (2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026).

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title = "High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance",

abstract = "In this work, we present AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MIS-HEMTs) with an AlN/Al2O3 gate dielectric intended for high-voltage GaN power applications with low dynamic ON-resistance (RON) and stable threshold voltage (Vth). The high-quality plasma-enhanced atomic layer deposition (PEALD) AlN insert layer effectively reduces interface traps and suppresses charge trapping effects, enabling the MIS-HEMTs to exhibit a low dynamic RON degradation of only 2.77 times after 300 ms drain bias stress, significantly lower than the 4.2 times observed in conventional Al2O3 gate stacks. Under negative bias temperature instability (NBTI) stress with VGS = -16 V for 104 s, the Vth shift is less than 0.14 V, indicating superior reliability under long-term negative gate bias. Furthermore, a negligible Vth shift is observed under positive gate bias conditions.",

keywords = "AlN, Dynamic R, Interface Trap Density, MIS-HEMT, NBTI, Reliability",

author = "Jingyue Wu and Qiyi Guo and Xuanming Zhang and Jiachen Duan and Hao Wang and Jiangmin Gu and Wen Liu",

note = "Publisher Copyright: {\textcopyright} 2026 IEEE.; 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026 ; Conference date: 22-03-2026 Through 24-03-2026",

year = "2026",

doi = "10.1109/CSTIC68613.2026.11537913",

language = "English",

series = "2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Cor Claeys and Bin Yu and Beichao Zhang and Peng Bai and Qianqian Huang and Xiaowei Li and Liang, \{Steve X.\} and Hsiang-Lan Lung and Linyong Pang and Xinping Qu and Xiaoping Shi and Jianshi Tang and Pingqiang Zhou and Cheng Zhuo",

booktitle = "2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026",

}

Wu, J, Guo, Q, Zhang, X, Duan, J, Wang, H, Gu, J & Liu, W 2026, High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance. in C Claeys, B Yu, B Zhang, P Bai, Q Huang, X Li, SX Liang, H-L Lung, L Pang, X Qu, X Shi, J Tang, P Zhou & C Zhuo (eds), 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026. 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026, Institute of Electrical and Electronics Engineers Inc., 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026, Shanghai, China, 22/03/26. https://doi.org/10.1109/CSTIC68613.2026.11537913

High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance. / Wu, Jingyue; Guo, Qiyi; Zhang, Xuanming et al.
2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026. ed. / Cor Claeys; Bin Yu; Beichao Zhang; Peng Bai; Qianqian Huang; Xiaowei Li; Steve X. Liang; Hsiang-Lan Lung; Linyong Pang; Xinping Qu; Xiaoping Shi; Jianshi Tang; Pingqiang Zhou; Cheng Zhuo. Institute of Electrical and Electronics Engineers Inc., 2026. (2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

TY - GEN

T1 - High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance

AU - Wu, Jingyue

AU - Guo, Qiyi

AU - Zhang, Xuanming

AU - Duan, Jiachen

AU - Wang, Hao

AU - Gu, Jiangmin

AU - Liu, Wen

PY - 2026

Y1 - 2026

N2 - In this work, we present AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MIS-HEMTs) with an AlN/Al2O3 gate dielectric intended for high-voltage GaN power applications with low dynamic ON-resistance (RON) and stable threshold voltage (Vth). The high-quality plasma-enhanced atomic layer deposition (PEALD) AlN insert layer effectively reduces interface traps and suppresses charge trapping effects, enabling the MIS-HEMTs to exhibit a low dynamic RON degradation of only 2.77 times after 300 ms drain bias stress, significantly lower than the 4.2 times observed in conventional Al2O3 gate stacks. Under negative bias temperature instability (NBTI) stress with VGS = -16 V for 104 s, the Vth shift is less than 0.14 V, indicating superior reliability under long-term negative gate bias. Furthermore, a negligible Vth shift is observed under positive gate bias conditions.

AB - In this work, we present AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MIS-HEMTs) with an AlN/Al2O3 gate dielectric intended for high-voltage GaN power applications with low dynamic ON-resistance (RON) and stable threshold voltage (Vth). The high-quality plasma-enhanced atomic layer deposition (PEALD) AlN insert layer effectively reduces interface traps and suppresses charge trapping effects, enabling the MIS-HEMTs to exhibit a low dynamic RON degradation of only 2.77 times after 300 ms drain bias stress, significantly lower than the 4.2 times observed in conventional Al2O3 gate stacks. Under negative bias temperature instability (NBTI) stress with VGS = -16 V for 104 s, the Vth shift is less than 0.14 V, indicating superior reliability under long-term negative gate bias. Furthermore, a negligible Vth shift is observed under positive gate bias conditions.

KW - AlN

KW - Dynamic R

KW - Interface Trap Density

KW - MIS-HEMT

KW - NBTI

KW - Reliability

UR - https://www.scopus.com/pages/publications/105042249321

U2 - 10.1109/CSTIC68613.2026.11537913

DO - 10.1109/CSTIC68613.2026.11537913

M3 - Conference Proceeding

AN - SCOPUS:105042249321

T3 - 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026

BT - 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026

A2 - Claeys, Cor

A2 - Yu, Bin

A2 - Zhang, Beichao

A2 - Bai, Peng

A2 - Huang, Qianqian

A2 - Li, Xiaowei

A2 - Liang, Steve X.

A2 - Lung, Hsiang-Lan

A2 - Pang, Linyong

A2 - Qu, Xinping

A2 - Shi, Xiaoping

A2 - Tang, Jianshi

A2 - Zhou, Pingqiang

A2 - Zhuo, Cheng

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026

Y2 - 22 March 2026 through 24 March 2026

ER -

Wu J, Guo Q, Zhang X, Duan J, Wang H, Gu J et al. High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance. In Claeys C, Yu B, Zhang B, Bai P, Huang Q, Li X, Liang SX, Lung HL, Pang L, Qu X, Shi X, Tang J, Zhou P, Zhuo C, editors, 2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026. Institute of Electrical and Electronics Engineers Inc. 2026. (2026 Conference of Science and Technology of Integrated Circuits, CSTIC 2026). doi: 10.1109/CSTIC68613.2026.11537913

High-Quality PEALD-AlN Insert Layer in MIS-HEMT with Negligible NBTI and Low Dynamic ON-resistance

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Publication series

Conference

Keywords

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