High ION/IOFF Ratio > 105 Ag-Gated E-Mode GaN p-FETs Enabled by p++-GaN Contact and Polarization-Enhanced AlN Layer

Zhiwei Sun, Hao Tian, Weisheng Wang, Xuanming Zhang, Maoqing Ling, Jie Zhang, Yinchao Zhao, Harm Van Zalinge, Ivona Z. Mitrovic, Kain Lu Low*, Sen Huang*, Wen Liu*

*Corresponding author for this work

Research output: Chapter in Book or Report/Conference proceedingConference Proceedingpeer-review

Abstract

This work reports the achievement of high-performance enhancement-mode GaN p-FETs on a novel epitax-ial structure. Through the optimization of the epitaxial structure, which includes a heavily doped p ++ -GaN contact layer and an ultra-thin AlN insertion layer, hole mobility and density are significantly enhanced, leading to a substantial reduction in sheet resistance (R_sh) I. As a result, a record-low contact resistance (R_c) of 2.17 Ω ⋯ mm and specific contact resistivity ρc) of 1.5 × 10-6 Ω ⋯ cm2 are achieved. Additionally, by using Ag as the Schottky gate, we successfully demonstrate Ag-gated p-FETs with a threshold voltage VTH) of -0.6 V, an ON-state current I_ON) of 6.7

Original languageEnglish
Title of host publicationProceedings of the 37th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2025
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages317-320
Number of pages4
ISBN (Electronic)9784886864413
DOIs
Publication statusPublished - 2025
Event37th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2025 - Kumamoto, Japan
Duration: 1 Jun 20255 Jun 2025

Publication series

NameProceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN (Print)1063-6854

Conference

Conference37th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2025
Country/TerritoryJapan
CityKumamoto
Period1/06/255/06/25

Keywords

  • Ag-gated p-FETs
  • CMOS
  • Enhancement-mode
  • GaN
  • Ohmic contacts
  • ratio

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