Abstract
— A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaNon-Si platform and verified by a series of designed tests.
| Original language | English |
|---|---|
| Pages (from-to) | 4162-4169 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 69 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 1 Aug 2022 |
| Externally published | Yes |
Keywords
- Bulk silicon substrate
- gallium nitride
- half bridge
- junction isolation (JI)
- power integration