Design and implementation of embedded multiprocessor architecture for underwater applications

Modern embedded multiprocessors are complex systems that often require years to design and verify. A significant factor is that engineers must allocate a disproportionate share of their effort to ensure that modern FPGA chips architecture behave correctly. This paper proposes a design and implementation of embedded multiprocessors architecture system focusing on its design area and performance. Proposed design presents challenges and opportunities that stem from task coarse granularity and the large number of inputs and outputs for each task. We have therefore designed a new architecture called embedded concurrent computing (ECC), which is implemented on an FPGA chip using VHDL. The performances of a realistic application show scalable speedups comparable to that of the simulation. The results show many data is gathered with the systems, such as size 18699 logic elements and maximum frequency 212 MHz. These data have been gathered by synthesis. Implementation has achieved by the provision of low complexities in terms of FPGA resource usage and frequency.