TY - GEN
T1 - A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation
AU - Karmani, Mouna
AU - Khedhiri, Chiraz
AU - Hamdi, Belgacem
AU - Man, Ka Lok
AU - Lim, Eng Gee
AU - Lei, Chi Un
PY - 2012
Y1 - 2012
N2 - As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.
AB - As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.
KW - Concurrent Error Detection (CED)
KW - Fault-tolerant systems
KW - Stuck-at fault model
KW - Transistor stuck-on fault model
KW - Transistor stuck-open fault model
KW - XOR-XNOR circuit
UR - https://www.scopus.com/pages/publications/84867459088
M3 - Conference Proceeding
AN - SCOPUS:84867459088
SN - 9789881925190
T3 - Lecture Notes in Engineering and Computer Science
SP - 1177
EP - 1180
BT - International MultiConference of Engineers and Computer Scientists, IMECS 2012
PB - Newswood Limited
T2 - 2012 International MultiConference of Engineers and Computer Scientists, IMECS 2012
Y2 - 14 March 2012 through 16 March 2012
ER -