A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things

Shenjian Zhang; Chun Zhao; Yuxin Guan; Kai Tang; Junyan Li; Rui Li; Yun Fang; Hao Gao

doi:10.1109/LASCAS64004.2025.10966373

A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things

Shenjian Zhang
, Chun Zhao
, Yuxin Guan
, Kai Tang
, Junyan Li
, Rui Li
, Yun Fang
, Hao Gao

Xi'an Jiaotong-Liverpool University
Jupiter Semi
Hunan University
Southeast University, Nanjing
Eindhoven University of Technology

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

Abstract

This work presents a compact multi-bit multi-order finite impulse response (FIR) digital-to-analog converter (DAC) design for internet of things (IoT). It is accomplished in 65-nm CMOS technology merging the 4-order FIR filter and 4-bit calibration-free DAC as one block. This FIR DAC achieves over -20-dB out-band noise filtering with 0-dBFS in-band signal input, and demonstrates a maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.26% and 0.12% in 502.5-mV full-scale range while consuming a power of 0.53-mW and occupying 0.052-mm2 area.

Original language	English
Title of host publication	2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798331522124
DOIs	https://doi.org/10.1109/LASCAS64004.2025.10966373
Publication status	Published - 2025
Event	16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025 - Bento Goncalves, Brazil Duration: 25 Feb 2025 → 28 Feb 2025

Publication series

Name	2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings

Conference

Conference	16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025
Country/Territory	Brazil
City	Bento Goncalves
Period	25/02/25 → 28/02/25

Keywords

digital-to-analog converter (DAC)
finite impulse response (FIR)
internet of things (IoT)
nonlinearity (NL)
signal-to-noise ratio (SNR)
signal-to-noise-and-distortion ratio (SINAD)

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10.1109/LASCAS64004.2025.10966373

Cite this

Zhang, S., Zhao, C., Guan, Y., Tang, K., Li, J., Li, R., Fang, Y., & Gao, H. (2025). A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things. In 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings (2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS64004.2025.10966373

Zhang, Shenjian ; Zhao, Chun ; Guan, Yuxin et al. / A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things. 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings).

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title = "A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things",

abstract = "This work presents a compact multi-bit multi-order finite impulse response (FIR) digital-to-analog converter (DAC) design for internet of things (IoT). It is accomplished in 65-nm CMOS technology merging the 4-order FIR filter and 4-bit calibration-free DAC as one block. This FIR DAC achieves over -20-dB out-band noise filtering with 0-dBFS in-band signal input, and demonstrates a maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.26\% and 0.12\% in 502.5-mV full-scale range while consuming a power of 0.53-mW and occupying 0.052-mm2 area.",

keywords = "digital-to-analog converter (DAC), finite impulse response (FIR), internet of things (IoT), nonlinearity (NL), signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SINAD)",

author = "Shenjian Zhang and Chun Zhao and Yuxin Guan and Kai Tang and Junyan Li and Rui Li and Yun Fang and Hao Gao",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025 ; Conference date: 25-02-2025 Through 28-02-2025",

year = "2025",

doi = "10.1109/LASCAS64004.2025.10966373",

language = "English",

series = "2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings",

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Zhang, S, Zhao, C, Guan, Y, Tang, K, Li, J, Li, R, Fang, Y & Gao, H 2025, A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things. in 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings. 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025, Bento Goncalves, Brazil, 25/02/25. https://doi.org/10.1109/LASCAS64004.2025.10966373

A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things. / Zhang, Shenjian; Zhao, Chun; Guan, Yuxin et al.
2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings).

Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review

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AU - Zhang, Shenjian

AU - Zhao, Chun

AU - Guan, Yuxin

AU - Tang, Kai

AU - Li, Junyan

AU - Li, Rui

AU - Fang, Yun

AU - Gao, Hao

PY - 2025

Y1 - 2025

N2 - This work presents a compact multi-bit multi-order finite impulse response (FIR) digital-to-analog converter (DAC) design for internet of things (IoT). It is accomplished in 65-nm CMOS technology merging the 4-order FIR filter and 4-bit calibration-free DAC as one block. This FIR DAC achieves over -20-dB out-band noise filtering with 0-dBFS in-band signal input, and demonstrates a maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.26% and 0.12% in 502.5-mV full-scale range while consuming a power of 0.53-mW and occupying 0.052-mm2 area.

AB - This work presents a compact multi-bit multi-order finite impulse response (FIR) digital-to-analog converter (DAC) design for internet of things (IoT). It is accomplished in 65-nm CMOS technology merging the 4-order FIR filter and 4-bit calibration-free DAC as one block. This FIR DAC achieves over -20-dB out-band noise filtering with 0-dBFS in-band signal input, and demonstrates a maximum integral nonlinearity (INL) and differential nonlinearity (DNL) of 0.26% and 0.12% in 502.5-mV full-scale range while consuming a power of 0.53-mW and occupying 0.052-mm2 area.

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KW - finite impulse response (FIR)

KW - internet of things (IoT)

KW - nonlinearity (NL)

KW - signal-to-noise ratio (SNR)

KW - signal-to-noise-and-distortion ratio (SINAD)

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BT - 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 16th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2025

Y2 - 25 February 2025 through 28 February 2025

ER -

Zhang S, Zhao C, Guan Y, Tang K, Li J, Li R et al. A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things. In 2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2025. (2025 IEEE 16th Latin American Symposium on Circuits and Systems, LASCAS 2025 - Proceedings). doi: 10.1109/LASCAS64004.2025.10966373

A Compact Multi-Bit Multi-Order FIR DAC Design for Internet of Things

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