Projects per year
Personal profile
Personal profile
Kain Lu Low holds Bachelor’s and Master’s degrees in Electrical and Computer Engineering from Purdue University, USA, and a PhD from the National University of Singapore. His research in computational semiconductor materials and device design within the DTCO framework has led to publications in acclaimed journals, such as IEEE Transactions on Electron Devices, and presentations at international conferences. Currently, Kain Lu is an associate professor at Xi’an Jiao Tong Liverpool University, focusing on innovations in semiconductor technologies from advanced materials and device perspectives. He previously held the same position at Shanghai Jiao Tong University from 2020 to 2023. In industry, he has been involved in developing circuit simulation software at a startup in Silicon Valley, California and served as a senior engineer at GLOBALFOUNDRIES in Singapore, focusing on Design Rule Checking (DRC), Layout Versus Schematic (LVS), and mask generation rules.
Education/Academic qualification
PhD, National University of Singapore
Master, Purdue University, USA
Bachelor, Purdue University, USA
Research areas
- Semiconductor
- TCAD Modeling
- Design-Technology Co-Optimization
- GaN semiconductor devices
- AI for semiconductor
- AI for TCAD
- Device physics
- Artificial Intelligence (AI)
- AI and Education
Person Types
- Staff
Expertise related to UN Sustainable Development Goals
In 2015, UN member states agreed to 17 global Sustainable Development Goals (SDGs) to end poverty, protect the planet and ensure prosperity for all. This person’s work contributes towards the following SDG(s):
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SDG 7 Affordable and Clean Energy
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Collaborations and top research areas from the last five years
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Projects
- 2 Active
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Advancing GaN CMOS Technology: Optimizing Device Performance and Design Efficiency through AI-Integrated TCAD Modeling
Low, K. L. (PI)
1/01/25 → 31/12/27
Project: Internal Research Project
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Development and Industrialization of High Performance Gallium Nitride Power Integrated Intelligent Chips
Gu, J. (Team member), Low, K. L. (Team member), Zhang, J. (Team member), Qi, Y. (Team member), Chen, H. (Team member), Li, J. (Team member), Hu, Y. (Team member) & Liu, W. (PI)
1/11/24 → 30/10/27
Project: Governmental Research Project
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787-V GaN-on-Si Quasi-Vertical Trench MOSFET with Thick Bottom SiO2
Ling, M., Li, J., Li, A., Hu, Z., Zhang, J., Sun, Z., Chen, Z., Guo, F., Zhang, P., Zalinge, H. V., Mitrovic, I. Z., Low, K. L., Huang, S., Yang, X., Shen, B. & Liu, W., May 2026, In: IEEE Transactions on Electron Devices. 73, 5, p. 2959-2966 8 p.Research output: Contribution to journal › Article › peer-review
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AgenticTCAD: A LLM-based Multi-Agent Framework for Automated TCAD Code Generation and Device Optimization
Fan, G., Ma, T., Sun, X., Wang, X., Low, K. L. & Shao, L., 4 Jun 2026, 2026 Design, Automation & Test in Europe Conference (DATE). Institute of Electrical and Electronics Engineers Inc.Research output: Chapter in Book or Report/Conference proceeding › Conference Proceeding › peer-review
Open Access -
A Sub-20 mV VTH Hysteresis Enhancement-mode GaN p-FET with PEALD AlON Gate Dielectric
Zhang, X., Duan, J., Ding, Y., Guo, Q., Wu, J., Liang, Y., Zhang, Y., Gu, J., Zhang, J., Mitrovic, I., Zalinge, H. V., Low, K. L., Huang, S. & Liu, W., 2026, (Accepted/In press) In: IEEE Electron Device Letters.Research output: Contribution to journal › Article › peer-review
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Atomic-scale oxygen engineering as a switching strategy for 2DEG: Evolution from p-GaN to GaON enabling non-destructive HEMT fabrication
Liu, Y., Duan, J., Zhang, J., Ling, M., Wen, J., Chen, X., Huang, S., Low, K. L., Zhang, P., van Zalinge, H. & Liu, W., Jun 2026, In: Materials Today Advances. 30, 100807.Research output: Contribution to journal › Article › peer-review
Open Access -
Descriptor: Emerging Semiconductor Device Electrical Dataset (ESDED)
Shen, F., Tang, R., Zhang, Q., Wang, C., Zhang, Y., Low, K. L. & Li, Y., 12 Feb 2026, In: IEEE Data Descriptions. 3, p. 132-139 8 p.Research output: Contribution to journal › Article › peer-review
Open Access
Activities
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Frontier Seminar on AI-Enabled Semiconductor Design and GaN RF Technology
Low, K. L. (Speaker)
27 Apr 2026Activity: Talk or presentation › Keynote Speech
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IEEE CASS-EDS Suzhou–Wuhan Outreach Workshop 2025 GaN Innovation for Power Electronics Applications & Collaboration
Low, K. L. (Speaker)
19 Dec 2025Activity: Talk or presentation › Invited talk
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2nd Sino-Malaysia CASS Workshop: AI-Enhanced and Physics-Guided Framework for Accelerated Device Development and Design-Technology Co-Optimization
Low, K. L. (Speaker)
25 Nov 2025 → 26 Nov 2025Activity: Talk or presentation › Invited talk
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Colloquium on Industry–Academia–Research Collaborative Innovation in GaN Technology
Low, K. L. (Organiser)
11 Jul 2025Activity: Participating in or organising an event › Organising an event e.g. a conference, workshop, …
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Workshop Series on TCAD Device and Process Simulation: Theory, Hands-On Practice, and Applications
Low, K. L. (Speaker)
10 Jul 2025 → 25 Jul 2025Activity: Talk or presentation › Presentation at conference/workshop/seminar